1. Field of the Invention
The present invention relates to a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory), and more particularly to a data interface device for accessing an SDRAM that can address a phase problem between a clock and data incurable at a high-speed SDRAM access time.
2. Description of the Related Art
FIG. 1 is a schematic diagram illustrating a typical connection state of a data bus and a clock for an SDRAM (Synchronous Dynamic Random Access Memory) interface. A timing diagram associated with FIG. 1 is shown in FIG. 2. Input PADs 3 and 5 and output PADs 4 and 6 are provided between an SDRAM 1 and a memory controller 2. As shown in FIG. 2, it can be seen that a board clock is measured between the PAD 3 of the SDRAM 1 and the PAD 6 of the memory controller 2, and that board DATA is measured between the PAD 4 of the SDRAM 1 and the PAD 5 of the memory controller 2. That is, when an internal clock is outputted from the PAD 6 of the memory controller 2, and then changed to a board level signal, it can be seen that data inputted to the memory controller 2 has larger delay in comparison with the internal clock produced by the memory controller 2. This delay can be different according to various elements such as voltage, temperature, board state, etc. FIG. 3 shows larger delay as compared with FIG. 2. The SDRAM 1 outputs data at a rising edge of the board clock. Here, the board clock is the same as the board level signal based on the internal clock. As shown in FIGS. 2 and 3, as a phase of the board clock for driving the SDRAM 1 is slower than a phase of the internal clock, data outputted from the SDRAM 1 synchronized with the board clock and then inputted to the memory controller 2, has larger delay in comparison with the internal clock.
When delay of a signal such as a clock or data is large, a time point of inputting internal DATA into the memory controller 2 can be the same as a time point of a rising edge of the internal clock as indicated by “V” in FIG. 3. That is, when the internal DATA is used with the internal clock, setup or hold violation can be incurred. To prevent this violation, there is present a method using a negative edge of the internal clock. However, the method has a problem in that data may be inputted at a time point of the negative edge of the internal clock as delay in the method is smaller than delay in FIG. 3.
That is, this phenomenon occurs because a relationship between the internal clock and the data input is asynchronous. When the phenomenon cannot be removed, an operating frequency must be lowered according to an operating state, such that the lowered operating frequency may have a negative effect on the performance of a device.
In many methods for preventing the negative effect, a DLL (Delay Locked Loop) circuit 7 is used as shown in FIG. 4. When the DLL circuit 7 is used, externally inputted data can be predicted to some degree because an external clock (i.e., a board clock) and an internal clock can be matched to each other. Consequently, the above-described asynchronous problem can be avoided. In particular, there are problem in that a design of the DLL circuit 7 requires complicated technology differently from general circuits and it is very difficult for replica delay in PADs, pins, etc. to be predicted.